| 000 -LEADER |
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| fixed length control field |
06272nam a2200709 i 4500 |
| 001 - CONTROL NUMBER |
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| control field |
EBC1911666 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
MiAaPQ |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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| fixed length control field |
cr cnu|||||||| |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
150124s2015 nyua foab 001 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9781606505137 |
| Qualifying information |
electronic |
|
|---|
| Cancelled/invalid ISBN |
9781606505120 |
| Qualifying information |
print |
| 024 7# - OTHER STANDARD IDENTIFIER |
|---|
| Canceled/invalid standard number or code |
10.5643/9781606504871 |
| Source of number or code |
doi |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(OCoLC)900732839 |
|
|---|
| System control number |
(CaBNvSL)swl00404623 |
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| System control number |
(MiAaPQ)EBC1911666 |
|
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| System control number |
(Au-PeEL)EBL1911666 |
|
|---|
| System control number |
(CaPaEBR)ebr11007948 |
|
|---|
| System control number |
(CaONFJC)MIL688595 |
|
|---|
| System control number |
(OCoLC)900898190 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
MiAaPQ |
| Language of cataloging |
eng |
| Description conventions |
rda |
| -- |
pn |
| Transcribing agency |
MiAaPQ |
| Modifying agency |
MiAaPQ |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
TK7874.75 |
| Item number |
.G646 2015 |
| 082 0# - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.395 |
| Edition number |
23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Goel, Ashok K., |
| Dates associated with a name |
1953-, |
| Relator term |
author. |
| 245 12 - TITLE STATEMENT |
|---|
| Title |
A one-semester course in modeling of VLSI interconnections / |
| Statement of responsibility, etc |
Ashok K. Goel. |
| 264 #1 - |
|---|
| -- |
New York, [New York] (222 East 46th Street, New York, NY 10017) : |
| -- |
Momentum Press, |
| -- |
2015. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
1 online resource (xv, 340 pages) : |
| Other physical details |
illustrations. |
| 336 ## - |
|---|
| -- |
text |
| -- |
rdacontent |
| 337 ## - |
|---|
| -- |
computer |
| -- |
rdamedia |
| 338 ## - |
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| -- |
online resource |
| -- |
rdacarrier |
| 490 1# - SERIES STATEMENT |
|---|
| Series statement |
Electronic circuits and semiconductor devices collection, |
| International Standard Serial Number |
2376-4848 |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc |
Includes bibliographical references and index. |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
1. Introductory concepts -- 1.1 Metallic interconnections -- 1.2 Simplified modeling of resistive interconnections as ladder networks -- 1.3 Propagation modes in a metallic interconnection -- 1.4 Slow-wave mode -- 1.5 Propagation delays -- |
|
|---|
| Formatted contents note |
2. Modeling of interconnection resistances, capacitances, and inductances -- 2.1 Interconnection resistance -- 2.2 Modeling of resistance for a copper interconnection -- 2.3 Interconnection capacitances -- 2.4 The Green's function method, Method of images -- 2.5 Green's function method, Fourier integral approach -- 2.6 Interconnection inductances -- 2.7 Inductance extraction using FastHenry -- 2.8 Approximate equations for capacitances -- 2.9 Approximate equations for interconnection capacitances and inductances on silicon and GaAs substrates -- |
|
|---|
| Formatted contents note |
3. Modeling of interconnection delays -- 3.1 Metal-insulator-semiconductor microstrip line model of an interconnection -- 3.2 Transmission line analysis of single-level interconnections -- 3.3 Transmission line model for multilevel interconnections -- 3.4 Modeling of parallel and crossing interconnections -- 3.5 Modeling of very-high-frequency losses in interconnections -- 3.6 Compact modeling of interconnection delays -- 3.7 Modeling of active interconnections -- |
|
|---|
| Formatted contents note |
4. Modeling of interconnection crosstalk -- 4.1 Lumped capacitance model -- 4.2 Coupled multiconductor MIS microstrip line model -- 4.3 Frequency-domain model analysis of single-level interconnections -- 4.4 Transmission line analysis of parallel multilevel interconnections -- 4.5 Compact expressions for crosstalk analysis -- |
|
|---|
| Formatted contents note |
5. Modeling of electromigration-induced interconnection failure -- 5.1 Electromigration factors and mechanism -- 5.2 Problems caused by electromigration -- 5.3 Reduction of electromigration -- 5.4 Measurement of electromigration -- 5.5 Electromigration in the copper interconnections -- 5.6 Models of integrated circuit reliability -- 5.7 Modeling of electromigration due to current pulses -- 5.8 Guidelines for testing electromigration -- |
|
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| Formatted contents note |
6. Other interconnection technologies -- 6.1 Optical interconnections -- 6.2 Superconducting interconnections -- 6.3 Nanotechnology circuit interconnections -- |
|
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| Formatted contents note |
Appendixes -- A. Tables of constants -- B. Method of images -- C. Method of moments -- D. Transmission line equations -- E. Miller's theorem -- F. Inverse Laplace transformation technique -- Index. |
| 506 ## - RESTRICTIONS ON ACCESS NOTE |
|---|
| Terms governing access |
Restricted to libraries which purchase an unrestricted PDF download via an IP. |
| 520 3# - SUMMARY, ETC. |
|---|
| Summary, etc |
Quantitative understanding of the parasitic capacitances and inductances and the resultant propagation delays and crosstalk phenomena associated with the metallic interconnections on the very large scale integrated (VLSI) circuits has become extremely important for the optimum design of the state-of-the-art integrated circuits. It is because more than 65 percent of the delays on the integrated circuit chip occur in the interconnections and not in the transistors on the chip. Mathematical techniques to model the parasitic capacitances, inductances, propagation delays, crosstalk noise, and electromigration-induced failure associated with the interconnections in the realistic high-density environment on a chip will be discussed. An overview of the future interconnection technologies for the nanotechnology circuits will also be presented. This book will be the first book of its kind written for a one-semester course on the mathematical modeling of metallic interconnections on a VLSI circuit. In most institutions around the world offering BS, MS, and Ph.D. degrees in Electrical and Computer Engineering, such a course will be suitable for the first-year graduate students and it will also be appropriate as an elective course for senior level BS students. This book will also be of interest to practicing engineers in the field who are looking for a quick refresher on this subject. |
| 588 ## - |
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| -- |
Title from PDF title page (viewed on January 24, 2015). |
| 590 ## - LOCAL NOTE (RLIN) |
|---|
| Local note |
Electronic reproduction. Ann Arbor, MI : ProQuest, 2015. Available via World Wide Web. Access may be limited to ProQuest affiliated libraries. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Integrated circuits |
| General subdivision |
Very large scale integration |
| -- |
Mathematical models. |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
VLSI |
|
|---|
| Uncontrolled term |
Integrated Circuits |
|
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| Uncontrolled term |
Interconnections |
|
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| Uncontrolled term |
Copper Interconnections |
|
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| Uncontrolled term |
Propagation Delays |
|
|---|
| Uncontrolled term |
Crosstalk |
|
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| Uncontrolled term |
Modeling |
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| Uncontrolled term |
Electromigration |
|
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| Uncontrolled term |
Capacitances |
|
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| Uncontrolled term |
Inductances |
|
|---|
| Uncontrolled term |
Nanotechnology |
| 655 #4 - INDEX TERM--GENRE/FORM |
|---|
| Genre/form data or focus term |
Electronic books. |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Display text |
Print version: |
| International Standard Book Number |
9781606505120 |
| 797 2# - LOCAL ADDED ENTRY--CORPORATE NAME (RLIN) |
|---|
| Corporate name or jurisdiction name as entry element |
ProQuest (Firm) |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
|---|
| Uniform title |
Electronic circuits and semiconductor devices collection. |
| -- |
2376-4848 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Uniform Resource Identifier |
https://ebookcentral.proquest.com/lib/kliuc-ebooks/detail.action?docID=1911666 |
| Public note |
Click to View |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
|
| Koha item type |
E-book |
