Verification by error modeling [electronic resource] : using testing techniques in hardware verification / written by Katarzyna Radecka, Zeljko Zilic.
By: Radecka, Katarzyna.
Contributor(s): Zilic, Zeljko | ebrary, Inc.
Material type:
BookSeries: Frontiers in electronic testing: 25.Publisher: Boston : Kluwer Academic Publishers, 2003Description: xiv, 216 p. : ill.Subject(s): Integrated circuits -- Very large scale integration -- Computer-aided design | Integrated circuits -- Verification | Error analysis (Mathematics)Genre/Form: Electronic books.DDC classification: 621.39/5 Online resources: An electronic book accessible through the World Wide Web; click to view
| Item type | Current location | Collection | Call number | URL | Copy number | Status | Date due | Item holds |
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E-book
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IUKL Library | Subscripti | http://site.ebrary.com/lib/kliuc/Doc?id=10088540 | 1 | Available |
Total holds: 0
Includes bibliographical references and index.
Electronic reproduction. Palo Alto, Calif. : ebrary, 2013. Available via World Wide Web. Access may be limited to ebrary affiliated libraries.
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